This invention relates in general to clock doubler circuits and in particular, to a clock signal frequency doubler circuit with externally selectable duty cycle control.
Clock doubler circuits are particularly useful in computer systems requiring two or more clock signals of different frequencies. For example, a memory controller interfacing with a dynamic random-access-memory ("DRAM") typically needs control signals that run at twice the frequency of a system clock. Accordingly, computer systems employing such memory controllers require at least two clock signals, the system clock signal and another clock signal running at twice the frequency of the system clock signal.
There are many well known techniques for generating two or more clock signals of different frequencies from a single clock signal. A first type of techniques starts with the highest frequency clock signal and generates the other clock signals from the highest frequency clock signal using, for example, frequency dividers. For example, a computer system using one of these first type of techniques may receive a clock signal that is twice the frequency of a system clock signal, and generate the system clock signal by passing the received signal through a divide-by-two frequency divider included in the computer system.
Conversely, a second type of techniques starts with a lower or the lowest frequency clock signal and generates the higher frequency clock signals from the lower frequency clock signal using, for example, phase-locked-loop circuits. For example, a computer system using one of these second type of techniques may receive the system clock signal, and generate a clock signal that is twice the frequency of the system clock signal by passing the received system clock signal through a phase-locked-loop circuit included in the computer system. Although the second type of techniques may be preferable for system design, they are also generally more difficult to implement.
When generating a clock signal that is twice the frequency of a system clock signal from the system clock signal, it may also be desirable to be able to vary the duty cycle of the generated clock signal. For example, in certain applications it may be desirable to generate a clock signal that is not only twice the frequency of a system clock signal, but also has a 50% duty cycle. In other applications, it may be desirable to generate a clock signal having 40% or 60% duty cycles. In addition, it may be desirable to control such duty cycle variation from a source such as a host processor, which is separate or external from the clock generation circuit that generates the clock signal that is twice the frequency of a system clock signal from the system clock signal.